View X9271-27_3375947.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn8174.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copy right intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x9271 single supply/low powe r/256-tap/spi bus single digitally-c ontrolled (xdcp?) potentiometer features ? 256 resistor taps spi serial interface for write, read, and transfer operations of the potentiometer wiper resistance, 100 ? typical @ v cc = 5v 16 nonvolatile data registers nonvolatile storage of multiple wiper positions power-on recall. loads saved wiper position on power-up. standby current < 3a max v cc : 2.7v to 5.5v operation 50k ? , 100k ? versions of end to end resistance 100 yr. data retention endurance: 100,000 data changes per bit per register 14-lead tssop low power cmos description the x9271 integrates a single digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digital controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. the potentiometer has associated with it a volatile wiper counter register (wcr) and a four nonvolatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. powerup recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram 50k ? and 100k ? r h r l r w pot v cc v ss spi bus power-on recall wiper counter register (wcr) data registers 16 bytes interface bus interface and control address data status write read transfer inc/dec control 256-taps data sheet march 31, 2005
2 fn8174.1 march 31, 2005 detailed functional diagram circuit level applications ? vary the gain of a voltage amplifier provide programmable dc reference voltages for comparators and detectors control the volume in audio circuits trim out the offset voltage error in a voltage amplifier circuit set the output voltage of a voltage regulator trim the resistance in wheatstone bridge circuits control the gain, characteristic frequency and q-factor in filter circuits set the scale factor and zero point in sensor signal conditioning circuits vary the frequency and duty cycle of timer ics vary the dc biasing of a pin diode attenuator in rf circuits provide a control variable (i, v, or r) in feedback circuits system level applications adjust the contrast in lcd displays control the power level of led transmitters in communication systems set and regulate the dc biasing point in an rf power amplifier in wireless systems control the gain in audio and home entertainment systems provide the variable dc bias for tuners in rf wireless systems set the operating points in temperature control systems control the operating point for sensors in industrial systems trim offset and gain errors in artificial intelligent systems r 0 r 1 r 2 r 3 wiper counter register (wcr) r h r l data r w interface and control circuitry v cc v ss bank 0 r 0 r 1 r 2 r 3 bank 1 r 0 r 1 r 2 r 3 bank 2 r 0 r 1 r 2 r 3 bank 3 12 additional nonvolatile registers 3 banks of 4 registers x 8-bits cs sck a0 so si hold wp a1 control 256-taps 50k ? and 100k ? power-on recall x9271
3 fn8174.1 march 31, 2005 pin configuration pin assignments v cc r l v ss 1 2 3 4 5 6 7 8 14 13 12 11 10 9 a0 r w sck cs tssop r h x9271 s0 nc si hold wp a1 tssop symbol function 1 so serial data output. 2 a0 device address. 3 nc no connect. 4cs chip select. 5 sck serial clock. 6 si serial data input. 7v ss system ground. 8wp hardware write protect. 9 a1 device address. 10 hold device select. pause the serial bus. 11 r w wiper terminal of the potentiometer. 12 r h high terminal of the potentiometer. 13 r l low terminal of the potentiometer. 14 v cc system supply voltage. x9271
4 fn8174.1 march 31, 2005 pin descriptions bus interface pins s erial o utput (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. s erial i nput si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. s erial c lock (sck) the sck input is used to clock data into and out of the x9271. h old (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. cmos level input. d evice a ddress (a1 - a0) the address inputs are used to set the the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communic ation with the x9271. c hip s elect (cs ) when cs is high, the x9271 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. cs low enables the x9271, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins h ardware w rite p rotect i nput (wp ) the wp pin when low prevents nonvolatile writes to the data registers. n o c onnect . no connect pins should be left floating. this pins are used for intersil manufacturing and testing purposes. x9271
5 fn8174.1 march 31, 2005 principles of operation device description s erial i nterface the x9271 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. a rray d escription the x9271 is comprised of a resistor array (see figure 1). the array contains the equivalent of 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are controlled by a wiper counter register (wcr). the 8-bits of the wcr (wcr[7:0]) are decoded to select, and enable, one of 256 switches (see table 1). p ower - up and d own r ecommendations . there are no restrictions on the power-up or power- down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate specification is always in effect. figure 1. detailed potentiometer block diagram serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn r h r l r w 8 8 c o u n t e r d e c o d e if wcr = 00[h] then r w = r l if wcr = ff[h] then r w = r h wiper (wcr) bank_0 only (dr0) (dr1) (dr2) (dr3) x9271
6 fn8174.1 march 31, 2005 device description wiper counter register (wcr) the x9271 contains a wiper counter register for the dcp potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modified one step at a time by the increment/ decrement instruction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9271 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the r0 value into the wcr. the dr0 value of bank 0 is the default value. data registers (dr3?dr0) the potentiometer has four 8-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvol atile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. bits [7:0] are used to store one of the 256 wiper positions or data (0 ~255). status register (sr) this 1-bit status register is used to store the system status. wip: write in progress status bit, read only. ? when wip=1, indicates that high-voltage write cycle is in progress. ? when wip=0, indicates that no high-voltage write cycle is in progress table 1. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile, v). table 2. data register, dr (8-bit), dr[7:0]: used to store wiper positions or data (nonvolatile, nv). table 3. status register, sr (wip is 1-bit) wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvv (msb) (lsb) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 nv nv nv nv nv nv nv nv msb lsb wip (lsb) x9271
7 fn8174.1 march 31, 2005 device description instructions i dentification b yte (id and a) the first byte sent to the x9271 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the slave address are a device type identifier. the id[3:0] bits is the device id for the x9271; this is fixed as 0101[b] (refer to table 4). the a1 - a0 bits in the id byte is the internal slave address. the physical device address is defined by the state of the a1 - a0 input pins. the slave address is externally specified by the user. the x9271 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9271 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a1 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . i nstruction b yte (i[3:0]) the next byte sent to the x9271 contains the instruction and register poin ter information. the three most significant bits are used provide the instruction opcode (i[3:0]). the rb and ra bits point to one of the four data registers. p0 is the pot selection; since the x9271 is single pot, the p0=0. the format is shown in ta bl e 5 . r egister b ank s election (r1, r0, p1, p0) there are 16 registers organized into four banks. bank 0 is the default bank of registers. only bank 0 registers can be used for data register to wiper counter register operations. banks 1, 2, and 3 are additional banks of registers (12 total) that can be used for spi write and read operations. the data registers in banks 1, 2, and 3 cannot be used for direct read/write operations between the wiper counter register. register selection (dr0 to dr3) table register bank selection (bank 0 to bank 3) table table 4. identification byte format rb ra register selection operations 0 0 0 data register read and write; wiper counter register operations 0 1 1 data register read and write; wiper counter register operations 1 0 2 data register read and write; wiper counter register operations 1 1 3 data register read and write; wiper counter register operations p1 p0 bank selection operations 0 0 0 data register read and write; wiper counter register operations 0 1 1 data register read and write only 1 0 2 data register read and write only 1 1 3 data register read and write only id3 id2 id1 id0 0 0 a1 a0 0101 (msb) (lsb) device type identifier set to 0 for proper operation internal slave address x9271
8 fn8174.1 march 31, 2005 table 5. instruction byte format device description instructions five of the eight instructions are three bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the potentiometer; ? write wiper counter register ? change current wiper position of the potentiometer; ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. ? read status - this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the basic sequence of the three byte instructions is illustrated in figure 3. th ese three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a stat ic ram, with the static ram controlling the wiper positio n. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. the read status register instruction is the only unique format (see figure 4). two instructions require a two-byte sequence to complete (figure 2). these instructions transfer data between the host and the x9271; either between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter regist er to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. the final command is increment/decrement (figure 5 and 6). it is different from the other commands, because it?s length is indeterminate. once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tu ning capability to the host. for each sck clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the r l terminal. see instruction format for more details. write in process (wip bit) the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. i3 i2 i1 p0 rb ra p1 p0 (msb) (lsb) instruction opcode register selection pot selection (wcr selection) set to p0=0 for potentiometer operations p1 and p0 are used also for register bank selection for spi register write and read operations x9271
9 fn8174.1 march 31, 2005 figure 2. two-byte instruction sequence figure 3. three-byte instruction sequence (write) figure 4. three-byte instruction sequence (read) id3 id2 id1 id0 0 a1 a0 i3 i2 i1 rb ra p0 sck si cs 0101 device id internal instruction opcode address register 0 i0 0 p1 address pot/bank address 0 0 these commands only valid when p1 = p0 = 0 0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/bank address 00 p1 wcr[7:0] valid only when p1 = p0 = 0; or data register bit [7:0] for all values of p1 and p0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/bank address 00 p1 wcr[7:0] valid only when p1 = p0 = 0; s0 x x x xx xx x don?t care or data register bit [7:0] for all values of p1 and p0 x9271
10 fn8174.1 march 31, 2005 figure 5. increment/decrement instruction sequence figure 6. increment/decrement timing limits table 6. instruction set note: 1/0 = data is one or zero 0101 a1 a0 i3 i2 i1 i0 ra rb p0 scl si cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/bank address 00 p1 0 i n c 1 i n c 2 i n c n d e c 1 d e c n 0 instruction instruction set operation i3 i2 i1 i0 rb ra p 1 p 0 read wiper counter register 10010 0 01/0r ead the contents of the wiper counter register write wiper counter register 10100 0 01/0write new value to the wiper c ounter register read data register 10111/01/01/01/0r ead the contents of the data register pointed to by p1 - p0 and rb - ra write data register 11001/01/01/01/0write new value to the data register pointed to by p1 - p0 and rb - ra xfr data register to wiper counter register 11011/01/00 0transfer the contents of the data register pointed to by rb - ra (bank 0 only) to the wiper counter register xfr wiper counter register to data register 11101/01/00 0transfer the contents of the wiper c ounter register to the register pointed to by rb-ra (bank 0 only) increment/decrement wiper counter register 00100 0 0 0e nable increment/decrement of the wiper counter register read status (wip bit) 01010 0 0 1r ead the status of the internal write cycle, by checking the wip bit. sck si v w inc/dec cmd issued t wrid voltage out x9271
11 fn8174.1 march 31, 2005 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer wiper counter register (wcr) to data register (dr) cs falling edge device type identifier device addresses instruction opcode dr/bank addresses wiper position (sent by x9271 on so) cs rising edge 010100a1a010010000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode dr/bank addresses data byte (sent by host on si) cs rising edge 010100a1a010100000 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode dr/bank addresses data byte (sent by x9271 on so) cs rising edge 0 1 0 100a1a01011rbrap1 p0 d7d 6d5d4d3d2d1d0 cs falling edge device type identifier device addresses instruction opcode dr/bank addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0 1 0 1 0 0 a1a0 1 1 0 0 rbrap1 p0 d7d 6d5d4d3d2d1d0 cs falling edge device type identifier device addresses instruction opcode dr/bank addresses cs rising edge high-voltage write cycle 0 1 0 1 00a1a01110 rb ra 0 0 x9271
12 fn8174.1 march 31, 2005 transfer data register (dr) to wiper counter register (wcr) increment/decrement wiper counter register (wcr) read status register (sr) notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wcrx refers to wiper position data in the wiper counter register (2) ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). (4) ?x:?: don?t care. cs falling edge device type identifier device addresses instruction opcode dr/bank addresses cs rising edge 010100a1 a01101rbra0 0 cs falling edge device type identifier device addresses instruction opcode dr/bank addresses increment/decrement (sent by master on sda) cs rising edge 0 1 0 1 0 0 a1 a0 0 0 1 0 x x 0 0 i/d i/d . . . . i/d i/d cs falling edge device type identifier device addresses instruction opcode dr/bank addresses data byte (sent by x9271 on so) cs rising edge 010100a1a0 010100010000000 wip x9271
13 fn8174.1 march 31, 2005 absolute maximum ratings temperature under bias..................... -65 c to +135 c storage temperature ......................... -65 c to +150 c voltage on sck any address input with respect to v ss ................................. -1v to +7v ? v = |(v h - v l )|..................................................... 5.5v lead temperature (soldering, 10 seconds)........ 300 c i w (10 seconds)..................................................6ma comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog characteristics (over recommended industrial operating conditions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wi per voltage versus expected volt age as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to determine the actual c hange in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 255 or (r h - r l ) / 255, single pot (4) during power-up v cc > v h , v l , and v w . (5) n = 0, 1, 2, ?,255; m =0, 1, 2, ?., 254. symbol parameter limits test conditions min. typ. max. units r total end to end resistance 100 k ? t version r total end to end resistance 50 k ? u version end to end resistance tolerance 20 % power rating 50 mw 25 c, each pot i w wiper current 3 ma r w wiper resistance 300 ? i w = 3ma @ v cc = 3v r w wiper resistance 150 ? i w = 3ma @ v cc = 5v v term voltage on any r h or r l pin v ss v cc vv ss = 0v noise -120 dbv / hz ref: 1v resolution 0.4 % absolute linearity (1) 1 mi (3) r w(n)(actual) - r w(n)(expected) (5) relative linearity (2) 0.2 mi (3) r w(n + 1) - [r w(n) + mi ] (5) temperature coefficient of r total 300 ppm/ c ratiometric temp. coefficient 20 ppm/c c h /c l /c w potentiometer capacitancies 10/10/25 pf see macro model recommended operating conditions temp min. max. commercial 0 c+70 c industrial -40 c+85 c device supply voltage (v cc ) (4) limits x9271 5v 10% x9271-2.7 2.7v to 5.5v x9271
14 fn8174.1 march 31, 2005 d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) endurance and data retention capacitance power-up timing a.c. test conditions notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the spec ific instruction can be issued. these parameters are periodically sampled and not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 af sck = 2.5 mhz, so = open, v cc = 6v other inputs = v ss i cc2 v cc supply current (nonvolatile write) 15maf sck = 2.5mhz, so = open, v cc = 6v other inputs = v ss i sb v cc current (standby) 3 asck = si = v ss , addr. = v ss , cs = v cc = 6v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage v cc - 0.8 v i oh = -1ma, v cc +3v v oh output high voltage v cc - 0.4 v i oh = -0.4ma, v cc +3v parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c in/out (6) input / output capacitance (si) 8 pf v out = 0v c out (6) output capacitance (so) 8 pf v out = 0v c in (6) input capacitance (a0, cs , wp , hold , and sck) 6pfv in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms t puw (7) power-up to initiation of write operation 50 ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9271
15 fn8174.1 march 31, 2005 equivalent a.c. load circuit ac timing symbol parameter min. max. units f sck ssi/spi clock frequency 2.5 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 250 ns t v so output valid time 200 ns t ho so output hold time 0 ns t ro so output rise time 100 ns t fo so output fall time 100 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 10 ns t cs cs deselect time 2 s t wpasu wp , a0 setup time 0 ns t wpah wp , a0 hold time 0 ns 5v 1462 ? 100pf so pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 2714 ? 3v 1382 ? 100pf so pin 1217 ? x9271
16 fn8174.1 march 31, 2005 high-voltage write cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9271
17 fn8174.1 march 31, 2005 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo x9271
18 fn8174.1 march 31, 2005 xdcp timing (for all load instructions) write protect and device address pins timing ... cs sck si msb lsb vwx t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction) x9271
19 fn8174.1 march 31, 2005 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } } x9271
20 fn8174.1 march 31, 2005 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9271
21 fn8174.1 march 31, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 14-lead plastic, tssop, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x9271
22 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8174.1 march 31, 2005 ordering information device v cc limits blank = 5v 10% -2.7 = 2.7 to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = -40 c to +85 c package v = 14-lead tssop potentiometer organization pot u = 50k ? t = 100k ? x9271 v t v y x9271

▲Up To Search▲

Price & Availability of X9271-27

	To Download X9271-27 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .